1. Field of the Invention
The present invention generally relates to an analog integrated circuit layout, and more particularly to a floorplanning method for an analog integrated circuit layout using incremental floorplanning technique.
2. Description of Related Art
In modern analog design flow, the designers usually reuse previous designed circuits to reduce the complexity of designing new circuits for fast floorplan prototyping. Once technology or design migration is required in the new circuits, several components will need to follow complicated constraints such as fixed location, fixed shape, or change shape from rectilinear to rectangular. It is difficult for designers to refine the floorplan manually because of the lack of automation tools for analog designs.
To deal with the analog migration problem, there are many difficulties and constraints we will face with. For example, due to the internal design change, the shape of components will be changed, too. Once the shape of components is modified, the neighboring components should be adjusted to reflect the modification. Therefore, the manual adjustment task is difficult and time consuming.
Further, the relative locations of all the components present in the floorplan, which we call component topology, are designed to satisfy important electrical features such as current flow and routing plan. Therefore, the component topology must be maintained in order to preserve the electrical features.
Moreover, there usually exist some components which were wrongly designed in previous products, and must be corrected in the new circuits. For example, components such as differential pairs are restricted to be rectangular for its internal device matching. If the differential pairs were designed in a rectilinear shape rather than a rectangular shape, it should be corrected in the new design. This means some components will be modified from rectilinear to rectangular to hold their internal circuit properties and we call this constraint as rectangle constraint. Because the size of the chip will be determined in the early stage, the whole migration process must be completed under fixed-outline constraint.
Researchers have proposed several works to handle a few of the above constraints. However, none of these works considers all the constraints simultaneously. Therefore, a need has arisen to propose a novel floorplanning method for an analog integrated circuit layout for fast floorplan prototyping to overcome the aforementioned disadvantages.